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| PULSUS PS9604 Stereo, 24-Bit, 192kHz PCM-to-PWM Converter for Full Digital Power Amplifier Features Sampling Frequency: 32kHz to 192kHz 8X Oversampling at 96kHz 4X Oversampling at 192kHz Input Audio Data Word: 20-, 24-Bit 130 dB Dynamic Range 120 dB SNR (typical) Variable Modulation Index: 0.5 to 0.875 PWM Switching Frequency: 256~384kHz Variable PWM Mapping Method: Both Class AD, BD amplifications are supported Automatic Sample Rate Detection System Clock: 2048fs at 48kHz, 1024fs at 96kHz, 512fs at 192kHz Single 3.3 V Power Supply 28-Lead SOIC Package Description The PS9604 is a high performance, stereo, 24-bit, 192kHz PCM-to-PWM converter IC. The PS9604 uses a state-of-the-art digital signalprocessing algorithm to convert input PCM signal to PWM format without sacrificing the quality of audio signal. The PS9604 can be used with various 8X oversampling digital filters, for example, DF1704, SM5847, and PMD200. It can be set up to use different modulation indices and PWM mapping methods. The PS9604's excellent SNR and ultra-low distortion makes it suitable for a size-sensitive consumer power amplifier application where high performance is required, such as high-quality AV receiver, digital TV, and hi-fi amplifiers. A high-end quality full-digital amplifier can be built using the PS9604, with minimal cost. Application Block Diagram MOD-INDEX [1:0] EL 24/20BIT NS_MODE IM MUTE PWM Modulator PWM Modulator IN PWM_MAP [1:0] PWM_L+ PWM_LPWM_R+ PWM_RPower Supply VSS VDD A Gate Driver PR BCLK WCLK LDATA RDATA R Y H Bridge Serial Input Interface Multi-bit Delta-Sigma Modulator Gate Driver REF_CLK FS_CLK 192K 96K SF1 SF0 Sample Rate Detector Timing Generator RESET SYSCLK Copyright (c) Pulsus Technologies Inc. 2000 1 AUGUST 2000 REV0.4 PULSUS Specifications ABSOLUTE MAXIMUM RATINGS Parameter Power Supply Voltage (VDD to VSS) Input Current, (Any pin except Supply) Output Current (/Pin) Input Voltage (Any pin except 5V tolerant) Input Voltage (5V tolerant Input) Storage Temperature Min VSS - 0.3 VSS - 0.3 VSS - 0.3 -65 Max 4.0 10 30 VDD + 0.5 +7.5 +150 PS9604 Units V mA mA V V Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Parameter Power Supply Voltage (VDD to VSS) Input Voltage (Any pin except 5V tolerant) Input Voltage (5V tolerant Input) Ambient Operating Temperature Min 3.0 VSS -40 A Typ 3.3 Typ 50 50 - R Max 3.6 VDD 5.5 +85 Max 1 0.8 2.4 1.8 0.4 100 100 10 10 IN VSS Min -1 1.1 0.6 VDD - 0.4 20 20 2.0 2 ELECTRICAL CHARACTERISTICS Parameter Input Leakage Current IM Low-Level Input Voltage (except RESET) High-Level Input Voltage (RESET) Low-Level Input Voltage (RESET) EL High-Level Input Voltage (except RESET) High-Level Output Voltage (IO = 2mA) Low-Level Output Voltage (IO = 2mA) Pull-up Resistance PR Pull-down Resistance Input Capacitance (f = 1MHz, VDD = 0V) Output Capacitance (f = 1MHz, VDD = 0V) Copyright (c) Pulsus Technologies Inc. 2000 Y C Units V V V C Units A V V V V V V k k pF pF AUGUST 2000 REV0.4 PULSUS Pin Assignment PS9604 VDD BCLK WCLK LDATA RDATA SF1 SF0 96K 192K 1 2 3 4 5 6 7 8 9 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD PWM_R+ PWM_R24/20BIT REF_CLK 11 TEST_ENA 12 SYS_CLK 13 VSS 14 IM 3 FS_CLK 10 PR EL Copyright (c) Pulsus Technologies Inc. 2000 PS9604 (28Lead SOIC, Top View) IN VSS A M_INDEX1 M_INDEX0 RESET MUTE NS_MODE PWM_LPWM_L+ R PWM_MAP1 PWM_MAP0 AUGUST 2000 REV0.4 Y PULSUS Pin Descriptions PIN No. 1 PIN NAME VDD I/O Digital Power, +3.3V DESCRIPTION PS9604 5 RDATA IN 6 SF1 OUT 7 SF0 8 9 10 96K 192K PR 11 12 13 14 15 16 17 EL OUT IN FS_CLK REF_CLK IN TEST_ENA SYS_CLK IN VSS VSS PWM_L+ PWM_LOUT OUT IM OUT OUT Digital Ground Digital Ground 4 Sampling rate indication output. (SF1, SF0) = (0,0) : 44.1kHz (0,1) : other sampling rate (1,0) : 48kHz (1,1) : 32kHz 88.2/96kHz sampling rate indication output. This pin goes High when the sampling rate is 88.2/96kHz. 176.4/192kHz sampling rate indication output. This pin goes High when the sampling rate is 176.4/192kHz. Sampling rate clock input. This input is 5V tolerant. Internal pull-down resistor. Reference clock input. 12.288MHz Reference clock is required to detect sampling rate. This input is 5V tolerant. Internal pull-down resistor. Chip test mode enabling input. This pin should be tied to GND for normal operation. Master system clock input. Connect to an external clock source. 2048Fs at 32/44.1/48kHz sampling rate, 1024Fs at 88.2/96kHz sampling rate, 512Fs at 176.4/192kHz sampling rate. This input is 5V tolerant. Left channel Positive PWM output. Left channel Negative PWM output. AUGUST 2000 REV0.4 Copyright (c) Pulsus Technologies Inc. 2000 IN Right channel serial data input. Both LDATA and RDATA are assumed to be MSB-first 2's-compliment. If data is absent or held to a constant value (all 0's or constant values for 8192 words at 44.1/48kHz sampling rate), or any of the input clocks are removed, an internal MUTE is activated. This input is 5V tolerant. A 4 LDATA IN Left channel serial data input. This input is 5V tolerant. R 3 WCLK IN Word clock input for serial audio data. WCLK latch the shifted data input on the falling clock edge. This input is 5V tolerant. Y 2 BCLK IN Bit clock input for serial audio data. BCLK shifts data input on the rising clock edge. Need not run continuously; may be gated or used in a burst fashion. This input is 5V tolerant. PULSUS PS9604 Noise shaping mode selection. This pin selests between Noise shaping MODE0 (Low) and Noise shaping MODE1 (High). An internal 50k pull-up to VDD will hold NS_MODE high, so no connection is required if Noise shaping MODE1 is required. Internal pull-up resistor. Input must be driven by levels of VSS to VDD. Mute control. Active High input. Assert `High' to mute both stereo outputs. Deassert `Low' for normal operation. This input is 5V tolerant. Internal pull-down resistor. Reset input. Active Low Schmitt-Trigger input. The Schmitt-Trigger input allows a slowly-rising input to reset the chip reliably. The RESET signal must be asserted `Low' during power up. Deassert `High' for normal operation. This input is 5V tolerant. PWM mapping method selection. (PWM_MAP1, PWM_MAP0) = (0,0) : 400kHz, AD (0,1) : 800kHz, AD (1,0) : 400kHz, BD (1,1) : 400kHz, AD Internal pull-up resistor. Input must be driven by levels of VSS to VDD. Modulation Index selection. (M_INDEX1, M_INDEX0) = (0,0) : 50.0% (0,1) : 62.5% (1,0) : 75.0% (1,1) : 87.5% Internal pull-up resistor. Input must be driven by levels of VSS to VDD. 18 NS_MODE IN 19 MUTE IN 21 PWM_MAP0 IN 23 M_INDEX0 IN 24 M_INDEX1 25 24/20BIT 26 27 28 PR EL PWM_ROUT PWM_R+ VDD OUT - IM IN IN 5 Input data word size selection. This pin selects between 24 bits input word size (High) and 20 bits input word size (Low). An internal 50k pull-up to VDD will hold 24/20BIT high, so no connection is required if input word size is 24 bits. Internal pull-up resistor. Input must be driven by levels of VSS to VDD. Right channel Negative PWM output. Right channel Positive PWM output. Digital Power, +3.3V IN 22 PWM_MAP1 IN A Copyright (c) Pulsus Technologies Inc. 2000 R 20 RESET IN Y AUGUST 2000 REV0.4 PULSUS Package Dimensions PS9604 PR EL Copyright (c) Pulsus Technologies Inc. 2000 6 AUGUST 2000 REV0.4 IM IN A R Y |
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